1. Field of the Invention
The invention relates to memories made in the form of integrated circuits and more particularly to memories that include redundancy circuits.
An integrated memory comprises numerous memory cells in rows and columns on a very small surface area and a technical defect in one cell leads to the discarding of the entire memory. This is prevented by using redundancy circuits that are put into operation if a defect is observed when the memory is being tested.
2. Description of the Prior Art
Most usually, the memory will include several replacement rows or several replacement columns (or several rows and several columns at a time). Each replacement row or column can replace a defective row or column of the memory.
However, the replacement should be transparent to the user, i.e. the user should be capable of applying the address of the defective row or column to the input of the memory in order to read or write at this address just as if it were not defective. The address of the defective rows or columns is therefore recorded inside the integrated circuit; when the user presents a defective row or defective column address to the input of the memory, it is the internal circuits of the memory that recognize it as being one of the defective addresses recorded, and that route the electrical signals towards the replacement columns. The user plays no role in this process.
To record the defective addresses, devices broadly designated as "fuses" have been used and are still used: a fuse defines a piece of binary information according to its state (blank or programmed); for each defective address to be registered, a battery of several fuses is used, equal in number to the number of bits used to define an address. For an address of p bits, there is a battery of p fuses. The state, whether intact or programmed, of the different fuses of a battery defines an address of p bits. If there are N redundancy rows or columns, i.e. if it is desired that it should be possible to replace N defective rows or columns by replacement rows or columns, then N batteries are needed.
When there is need for a replacement element to replace a defective element, the address of this defective element is stored in a battery of fuses, and a validation fuse associated with this battery is "burned out" or "fused" to indicate that it is effectively used to define an operation of replacement.
The fuses may be physical fuses (for example an open circuit element that is converted into a short-circuit when it is fused, or the reverse); or again, as is more frequent now, the fuses may be non-volatile memory elements such as UPROM (unerasable programmable read-only memory) transistors. These transistors are electrically programmed and can no longer be erased. The blank state of the transistors corresponds to an original state of the "fuse"; the programmed state of the transistor corresponds to a "fused" state of the fuse.
FIG. 1 shows a part of a prior art redundancy circuit. This part is designed to store an address bit of a defective element and to compare the stored bit with a corresponding bit of the received address; the comparison of the received address and of the stored address defines whether there is any reason to put the redundancy into operation. There are therefore as many circuits like that of FIG. 1 as there are bits in the address of the defective element to be replaced.
The defective address bit is stored in a fuse consisting herein of an UPROM type floating-gate transistor TGF. The state of this transistor, whether blank or programmed, defines the value of the stored bit. A reading voltage VL is applied to the control gate of this transistor. If the transistor TGF has remained in the blank state (not programmed), it means that the stored address bit is a zero bit. In this case, the transistor TGF is conductive in the presence of the reading voltage VL. If, on the contrary, the transistor TGF has been programmed, the stored address bit is a 1; in this case, the transistor remains off despite the reading voltage VL.
A current-voltage converter constituted by a P channel transistor T1 and two inverters I1 and I2 is used to read the current flowing in the transistor TGF to determine whether it is on or off. This converter gives a logic 0 voltage level if the transistor TGF is on, hence if the stored bit is 0 and a logic 1 voltage level if the transistor TGF is off, hence if the stored bit is 1.
An exclusive-OR gate X1 receives, firstly, the output of the converter (output of I2) and, secondly, a bit A of the addressed received at a given instant by the memory. As indicated here above, if the applied address comprises p bits, then there are p circuits identical to that of FIG. 1, each circuit making a comparison between a received address bit Ai and a same-order i stored address bit. It is only if there is a bit-to-bit coincidence between the received address and the stored address that the redundancy will be put into operation.
If the received address bit is identical to the stored bit, the exclusive-OR element gives a logic 0. If not, it gives a 1. It is only if all the outputs of exclusive-OR elements corresponding to the different bits are at 0 that the redundancy should be put into operation. A NOR element, not shown, receives all the outputs S of the exclusive-OR elements and delivers a logic 1 only if all its inputs are simultaneously at 0. It furthermore receives an additional input corresponding to a validation fuse, this input being at 0 only if the validation fuse has been programmed.
More specifically, the current-voltage converter (T1, I1, I2) has a first inverter I1, the input of which is connected to a circuit node N1 which is the drain of the transistor TGF. The output of the inverter I1 is connected to the gate of a P channel transistor T1, the source of which is at a positive supply voltage Vdd and the drain of which is connected to the node N1. The relative dimensions of the transistor T1 and of the transistors constituting the inverter I1 make it possible to adjust the current thresholds that prompt the switching over of the inverter I1 in one direction or in another. The inverter I2, cascaded with the output of the inverter I1, is optional. In the present case, it inverts the output logic level of the inverter I1 to define a logic 0 level when the transistor TGF is blank and conductive.
Finally, to finish the description of FIG. 1, a transistor T2, controlled by a logic signal PW, is connected between the supply Vdd and the node N1. The signal PW is created by a power-on-reset circuit (not shown). This signal is conventionally generated some instants after the power is reset in the integrated circuit. It is used to establish a logic 1 level unambiguously at the node N1 after the power-on-reset operation when the transistor TGF is in a programmed state (hence a non-conductive state despite the reading voltage VL). Indeed, in this case, when the power is turned on again, the node N1 is floating (with TGF non-conductive). At the outset, its potential may be close to zero. This takes the output of the inverter I1 to 1 and confirms that the transistor T1 is off. The node N1 therefore remains floating and has no reason to tend towards 1 which, however, it should do to represent the programmed state of the transistor TGF. This is all the truer as there are substantial parasitic capacitances between the node N1 and the ground. To prevent this, the signal PW makes the transistor T2 unambiguously conductive for a brief instant, after the power has been reset, thus taking the node N1 to 1. The output of the inverter I1 goes to 0 and makes the transistor T1 conductive, then confirming the state 1 of the node N1 even after the disappearance of the signal PW.
One of the aims of the present invention is to avoid the need to use a power-on-reset signal PW. The circuit that produces this signal is indeed difficult to devise. It occupies much space and consumes substantial current.
In one approach, a capacitor has been placed between the output of the inverter I1 and the ground. If this capacitor is discharged at the power-on-reset operation, then it will tend to keep the transistor T1 conductive for a certain period of time during the power-on-reset operation and the node N1 will therefore have the time to rise to 1 by means of the transistor T1, after which the situation will be normal. Experience has shown that this approach is not satisfactory, firstly because the capacitor is bulky and secondly because it is difficult to adjust this capacitor in the technology of integrated circuits. There are uncertainties about its value and hence about its operation.
This is why, according to the invention, there is proposed a circuit that provides a satisfactory solution to this problem, especially by eliminating the need for a power-on-reset signal PW, in achieving this goal without downgrading the other characteristics of the circuit.
According to the invention, it is proposed to eliminate the transistor T2 and to place two additional inverters in series between the output of the inverter I1 and the gate of the transistor T1, each of these two additional inverters comprising two highly asymmetrical transistors, and the asymmetry being in the opposite direction for the two inverters.
This asymmetry is in a direction that tends to facilitate the operation of turning on the transistor T1 of the current converter.